1. Field of the Invention
The invention relates to a method of passivating and planarizing a metallization pattern on a semiconductor substrate.
2. Description Of The Prior Art
A metallization pattern for connecting components of integrated circuits can be fabricated by applying a metal layer to the full surface of a substrate and spin coating on to this layer a photoresist layer which is exposed through a mask in accordance with the desired metallization pattern. Subsequently, the photoresist is developed and finally, the areas of the metal coating not covered by the photoresist are etched off, yielding a metallization pattern for interconnections. The metallization pattern is then covered with an insulating layer on which a further metallization pattern is formed, which selectively contacts the underlying metallization pattern through via holes. The described sequence of process steps could be repeated one or several times to additionally generate one or several further metallization patterns.
Another prior art technique for generating metallization patterns is the so-called metal lift-off process which was described and claimed for the first time in U.S. Pat. No. 2,559,389. With this method, a polymer layer is applied to a substrate, and parts of this layer are removed from the substrate according to the metallization pattern required. Subsequently, a metal layer is applied to the full surface of the structure described, and the polymer with the metal covering it is selectively removed, leaving a metallization pattern in those areas where it was directly applied to the substrate.
With continued miniaturization of integrated circuits and increasing density, the conductive lines in the metallization patterns have been made narrower and denser. As a result of this, the planarity of the surface of the metallization system has become an essential factor in the manufacture of interconnection systems. The more often a metallization pattern is applied to a surface, the more irregular or non-planar the surface of the overlying, insulating layer becomes. Generally, after the application of three levels of metallization, the surface is so irregular that additional metallization layers can not be applied.
An irregular surface presents two problems which have a direct bearing on the yield and the reliability of the electronic components thus produced. When a metal layer is applied over an irregular surface, the resultant layer becomes thinner in those portions in which the underlying layer has a step. These thinned down portions result in current crowding and possible failure due to electron migration. A further problem relates to the forming of the resist pattern, since clear, distinct exposure becomes impossible as the surface irregularities increase. Accordingly, both the subtractive etching and the lift-off method, have failed to solve the problem of non-planarity of the layer surface.
German OS No. 2,430,692 describes a method of producing via holes in insulating layers, whereby the raised portions in the insulating quartz layer, which are caused by the conductive pattern, are reduced by cathode resputtering until the quartz layer in the area of the via holes to be produced has become perfectly planar. Cathode sputtering is adjusted in such a manner that the deposition rate of the insulating quartz layer is higher than the removal rate of said layer as a result of cathode resputtering. This method has the disadvantage that only conductive lines up to a width of about 5 .mu. can be planarized, i.e., the via holes between the first and the second metallization are limited to a diameter of that order. Furthermore, the aluminum surface is impaired by the high cathode resputtering rates, which results in flattened edges of the conductive lines after a cathode resputtering process in comparison with the edge shape after a lift-off process. Furthermore, over the second and third layer of the metallization pattern, the steps resulting from the broader and higher conductive lines can no longer be planarized in full, which often causes difficulties in the edge coverage both in the deep via holes between the second and the third layer and on the edges of the conductive lines.
German Patent Application No. P 26 15 862.3 describes a structure consisting of a substrate and at least one layer, in which the surfaces of the insulating material and the metallization pattern lie essentially in one plane. To produce this structure, a first layer of polyimide is applied to the substrate, to the polyimide layer a second layer of polysulfone is applied, to the polysulfone layer a thin layer of glass resin is applied, and finally to this third layer, a layer of photoresist is applied. The photoresist layer is exposed and developed in such a manner that the negative of the required pattern is obtained. Subsequently, the bared areas of the glass resin layer are removed by means of ion etching in a CF.sub.4 -atmosphere, and the underlying areas of the second and the first layer are removed by ion etching in an oxygen atmosphere. In a subsequent step, a conductive material of a thickness corresponding to the first polyimide layer is applied to the full surface of the structure. Then the structure is exposed to a solvent which dissolves the polysulfone, so that the overlying layers can be lifted off. In the resultant structure the metallization pattern is embedded in the polyimide layer, and the surfaces of the polyimide and the metallization pattern lie essentially in one plane. The process sequence described has to be repeated for generating the pattern of the via holes and for generating the next metallization pattern. However, this method has the disadvantage that it is very complex and elaborate. For generating the first metallization pattern, the pattern of the via holes and the second metallization pattern, metal has to be vapor deposited three times, so that two interfaces rather than one are formed. This necessarily leads to higher resistances in the via holes, since these are determined by the resistance on the interfaces.